Software tools are frequently used in the design of analog, mixed-signal and custom digital circuits. In front-end design-for-yield, designers must choose device sizes such that the maximum possible percentage of manufactured chips meet all specifications such as, e.g., gain greater than 60 B and a power consumption less than 1 mW. As such, the designers strive to maximize the yield of ECDs.
The design-for-yield problem of an ECD can easily include thousands of variables because there may be any number of devices in the ECD, each device having features of adjustable sizes, and being subject to any number of process variables, which are random in nature. The space of possible designs is very high as well, because there may be any number of design variables (variable dimensions or sizes) per device. Environmental variables such as, e.g., temperature and load conditions must be considered as well. Many of these effects can be simulated simultaneously in any suitable electronic circuit simulator such as, e.g., a Simulation Program with Integrated Circuit Emphasis (SPICE) software. However, the design problem is hard to decompose into simpler problems because the variables often have nonlinear interactions. All these variables impede a designer's ability to understand the issues affecting yield early in the design stage, and therefore his ability to choose device sizes that maximize yield.
In front-end design of ECDs, designers aim to choose a topology, i.e., devices such as transistors, and their associated sizes, according to pre-determined goals. In front-end design for yield, designers aim to set device sizes such that the maximum possible percentage of manufactured chips meets all performance specifications (i.e., maximize yield). Designers may even wish to further improve the ECD by increasing the margin of performance from specifications, e.g., by maximizing process capability (Cpk). A variety of tools can help the designer in achieving these goals. Such tools include simulators, schematic editors, optimizers, characterizers, and design environments.
Circuit simulators such as, e.g., a SPICE program, are typically used to estimate a design's performances, yield, and/or Cpk. Schematic editors offer a means for the designer to enter the topology into SPICE with visual feedback. Optimization tools, also known as optimizers, can automatically try out different device sizes and obtain feedback from estimations of circuit performance and yield from, for example, circuit simulation runs, and report the best designs to the user. Characterization tools, also known as characterizers, can gather and present, through a display module, ECD information to the user to aid his insight into the problem and, as such, allow the designer to seize opportunities for the design. Such characterization information can calculate the relative impact of design variables on yield, performance metrics as a function of design variable, or any other suitable characteristic value of the ECD. A design environment is a tool that can incorporates together other design tools, but its core characteristic is that it provides the designer a means to manage and try out different designs as efficiently and effectively as possible. The design environment thus serves, among other things, as a designer feedback and input tool. One way for the designer to choose circuit device sizes is to use a software-based optimization tool such as, for example, those described in Computer-Aided Design of Analog Integrated Circuits and Systems, R. Rutenbar, G. Gielen, and B. Antao, eds., IEEE Press, Piscataway, 2002. With feedback from a display module, the user sets up the optimization problem, invokes an optimization run, and monitors progress and results that get reported back via a database. Such a tool, whether applied ECDs or to multi-parameter designs (MPDs), incorporates an optimization algorithm that traverses the space of possible designs, obtains feedback about a cost function associated to candidate designs of the ECD (or MPD) through one or more simulators, or physical measurements, and returns the lowest-possible cost designs within finite time (e.g., overnight) and computer resource constraints (e.g., 5 CPUs available).
Optimization of ECDs can be challenging. The time required to simulate a single design point (also referred to as a candidate design, which includes a set of sizes attributable to devices of the ECD) at a single process corner/environmental point can take minutes or more. To estimate yield for a single design using Monte Carlo simulation can involve hundreds or more random samples from a process joint probability distribution function (jpdf). Further, simulations at several environmental points for each process point can be required. Therefore simulation can extend beyond several hours. This hinders the applicability of yield optimization using naïve Monte Carlo sampling (e.g., where the optimizer's cost function is −1.0*yield) because it would allow only a highly limited number of candidate designs to actually be examined within a reasonable time period. There are other challenges too: the cost function is generally a blackbox, which means that it is possibly nonconvex, possibly non-differentiable (and without easy access to derivatives), and possibly non-continuous. Such characteristics preclude the use of existing optimization algorithms that could otherwise take advantage of those properties. In other word, it is not possible to use algorithms that exploit numerous simplifying assumptions.
Similarly problems in yield optimization, or robust design, or stochastic optimization, exist in many technical fields beyond that of ECDs. In fact, such problems exist in almost any engineering field in which parameterizable design problems exist, for which simplifying assumptions cannot be made, and which have means of estimating a design's cost functions such as with a dynamical systems simulator. Such technical fields include, amongst others, automotive design, airfoil design, chemical process design, and robotics design.
A locally optimal design is one that has lower cost than all its immediate neighbors in design space. By contrast, a globally optimal design is one in which no other designs in the whole space are better. A robust optimization problem can be classified into global or local optimization, depending on whether a globally optimal solution is desired (or at least targeted) or, a locally optimal solution is sufficient. A convex mapping is one in which there is only one locally optimal design in the whole space, and therefore it is also the globally optimal design. Conversely, a nonconvex mapping means that there are more than one locally optimal designs in design space. The present disclosure is more related to problems in which convex mappings cannot be assumed, because they need more than local search algorithms to solve. Over the years, a wide variety of global blackbox algorithms have been developed, such as, for example, simulated annealing algorithms, evolutionary algorithms, tabu search, branch & bound algorithm, iterated local search, particle swarm optimization, and variants thereof. Local search algorithms are very numerous too and include, for example, Newton-method derivatives, gradient descent, derivative-free pattern search methods, etc.
In the field of yield optimization for transistor-precision circuits, most approaches make simplifying assumptions (e.g., by assuming linearity of constraints, or by modeling circuit performances with manually-set equations rather than simulation), or reduce the scope of the problem (e.g., by doing only local yield optimization rather than full global yield optimization, or by optimizing only on a few design variables rather than potentially hundreds). There is no approach that can do full global yield optimization on hundreds of variables with no simplifying assumptions.
With respect to ECD characterizers, there are just a few approaches that allow, but only in part, to capture and display mappings of design variables to performance metrics across the whole design space. One approach is merely to specify a center design point (center candidate design), and then to do a sweep of one or more design variables about that center design point, followed by simulating at each swept point. This is followed by displaying a circuit response as a function of a given variable's value, such as power versus w1 (width of transistor 1). This can be done for one or several corners, which have values for process and environmental points, e.g., nominal process point at a typical temperature and power supply setting, or for 50 Monte Carlo samples of process points on 3 environmental corners each. As an example, with Monte Carlo samples, a graph can show as the ordinate, statistical estimators such as yield, Cpk, or average value of a response (e.g. average power) with abscissa showing on of the circuit's variable. Of course, the ordinate can include several responses at once too.
A simplified version of this approach is merely perturbation analysis, in which for each design variable there are just one or two swept values with small perturbations from the center design variable point. These sweep approaches are good in that they give the user intuition of the circuit's response as a variable is changed. However, a major issue is that variable interactions are not captured. This can be a problem since interaction between design variables often matter in circuit design (i.e., circuit design problems are not linearly separable). A related approach is to sweep two design variables in all their combinations, to obtain a grid of candidate designs, then to simulate and display the response such as with a surface or contour plot. This can capture interactions of two variables at a time and give interesting insights. However, if there are N variables then there would be an order N2 interactions to simulate on a grid and plot, which can be prohibitively expensive. Furthermore, such a method ignores interactions of more than two variables. Additionally, the resolution of the grid would have a large effect on the number of simulations. For example, 5 values per variable would imply 25 samples (probably reasonable) for each two-variable interaction but is not enough resolution to be interesting, but a higher resolution of 10 samples per variable means 100 samples (probably unreasonable) for each two-variable interaction.
A third approach is to do space-filling sampling in the design variable range of interest, to simulate at those samples, build regression models which map design variables to performances (or yield, Cpk, etc) then, for two-dimensional and three-dimensional plots, to simulate off the model itself. The benefit of this latter approach is that it can capture interactions between design variables. It can also handle a large number of variables (hundreds or more) if the range of each variable is very small, or it can handle a broad ranges of design variables if there are few design variables (e.g. <10). However, the approach performs abysmally when the number of design variables is large and the range of each design variable is large. That is, the regression models capture the true mapping poorly because the mapping is highly nonlinear. More training samples are limited in the help they can provide because simulation time is not negligible. There is an upper bound on the number of simulation samples, typically 10,000 to 100,000, that can be for a larger circuit.
Another approach which tries to make better use of the simulation samples is called an active-learning approach in which only some samples and simulations are taken to start with, models are built in accordance with the samples and simulation, and then more samples and simulations are taken from the models' regions of highest uncertainty. The loop is then repeated. Unfortunately, these approaches introduce massive overhead in continual rebuilding of models, and the final models are often inaccurate. Finally, it is unclear how to incorporate statistical awareness into these characterization approaches in a general way. For example, for model-building approaches, adding process variables can imply a ten-time increase in the number of variables, which can be prohibitive when the number of input variables for a model has a strong impact on its ability to predict. The challenge that remains for characterization of MPD's, and ECD's in particular, is to capture and display mappings from design variables to performance, across the whole design space (where there can be hundreds of design variables), in reasonable time (e.g., in less than one day), in reasonable number of simulations (e.g., in less than 100,000 simulations), and including capturing design variable interactions, and other possible nonlinearities. Ideally, if the characterizer has uncertainties in its mappings, it would report these explicitly (and as intuitively as possible).
Existing circuit design environments have means for the user (designer) to invoke single-variable sweeps, perturbation analysis, two-variable grid sweeps, model-building characterization runs, optimization runs, and to get corresponding plots out. In communication with the design environments, are one or more circuit simulators. There is also, typically means to manually change design variable values, e.g. by typing new design variable values into a dialog box. Such circuit design environments have issues because the user cannot quickly get insight into the whole design at once. That is, if the user wants to understand the effect of sweeping one or more variables he has to invoke simulations, and wait for the responses. There is also the risk of obtaining candidate designs for local optima during design because the user may inadvertently focus on locally optimal regions, not knowing that better design regions of design variables space. In sum, current design environments' functionality for trying new designs has feedback, and the feedback offered is partial at best, causing inefficient and possibly suboptimal design.
In ECDs, there are many sorts of circuit types that are commonly reused, from differential pairs and current mirrors up to operational amplifiers, to name a few. Especially in the smallest blocks (also referred to as sub-blocks), designers find themselves spending considerable time finding the right sizes for the design, despite having designed such blocks possibly dozens or even hundreds of times before. The reason they keep redesigning these smallest blocks is that there can be slight variations in the ECD design problem. For example, different manufacturing processes can give rise to different transistor models; there can be different environmental conditions such as lowering power supply voltages; and there can be different specifications such as lowering power consumption targets. Furthermore, each block has a context within an ECD that can give rise to slightly different DC operating points. As such, continually redesigning such trivial circuits takes time, which could be better spent on more challenging design tasks if there were a means to design such sub-blocks more quickly. Optimizers can be used but the designer typically doesn't know exactly what specifications they want for each tiny block, and there is a tradeoff that can be explored before the user knows what he wants. Additionally, setting up an optimization (single- or multi-objective) can be more time-consuming than it would take the designer to just size the block or sub-block manually.
Therefore, it is desirable to provide four tools: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO should do global yield optimization on hundreds of variables with no simplifying assumptions. GSC should capture and display mappings from design variables to performance: across the whole design space, handle hundreds of design variables, in reasonable time (say <1 day), in reasonable number of simulations (say <100,000), capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties and intuitively display them. GSD should support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs. Block-specific design should make it trivial to design small circuit blocks, in a fashion that is palatable for designers (e.g. with less time & overhead than optimization).